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Quad, IEEE 802.3at/af PSE Controller
for Power-over-Ethernet
Event Registers (R02h–R08h)
Interrupt Mask Register (R01h)
The Interrupt Mask register (R01h, Table 7) contains
mask bits that suppress the corresponding interrupt
bits in register R00h (active-high). Setting mask bits low
individually disables the corresponding interrupt signal.
When masked (set low), the corresponding bits are still
set in the Interrupt register (R00h) but the masking bit
(R01h) suppresses the generation of an interrupt signal
( INT ). Supply interrupts set on a power-up or reset event
cannot be masked, such as TSD, V DD_UVLO , and V EE_
UVLO . On power-up or a reset condition, the Interrupt
Mask register is set to a default state of E4h if AUTO is
high, and 80h is AUTO is low.
Power Event Register (R02h/R03h)
The Power Event register (R02h/R03h, Table 8) records
changes in the power status of the port. On power-
up or after a reset condition, the Power Event reg-
ister is set to a default value of 00h. Any change in
PGOOD_ (R10h[7:4]) sets PG_CHG_ to 1. Any change in
PWR_EN_ (R10h[3:0]) sets PE_CHG_ to 1. PG_CHG_
and PE_CHG_ trigger on the transition edges of PGOOD_
and PWR_EN_, and do not depend on the actual logic
status of the bits. The Power Event register has two
addresses. When read through the R02h address, the
content of the register is left unchanged. When read
through the Clear on Read (CoR) R03h address, the
register content is reset to the default state.
Table 7. Interrupt Mask Register
ADDRESS = 01h
SYMBOL BIT NO.
TYPE
DESCRIPTION
SUP_MASK
TST_MASK
TCUT_MASK
CLS_MASK
DET_MASK
DIS_MASK
PG_MASK
PE_MASK
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Supply interrupt mask. A logic-high enables the SUP_INT interrupt. A logic-low
disables the SUP_INT interrupts.
Startup interrupt mask. A logic-high enables the TST_INT interrupt. A logic-low
disables the TST_INT interrupts.
Current interrupt mask. A logic-high enables the TCUT_INT interrupt. A logic-low
disables the TCUT_INT interrupt.
Classification interrupt mask. A logic-high enables the CLS_INT interrupt. A logic-low
disables the CLS_END interrupt.
Detection interrupt mask. A logic-high enables the DET_INT interrupt. A logic-low
disables the DET_INT interrupt.
DC disconnect interrupt mask. A logic-high enables the DIS_INT interrupts. A logic-
low disables the DIS_INT interrupts.
PGOOD interrupt mask. A logic-high enables the PG_INT interrupts. A logic-low
disables the PG_INT interrupts.
Power-enable interrupt mask. A logic-high enables the PE_INT interrupts. A logic-low
disables the PE_INT interrupts.
Table 8. Power Event Register
ADDRESS =
SYMBOL BIT NO.
02h
TYPE
03h
TYPE
DESCRIPTION
PG_CHG4
PG_CHG3
PG_CHG2
PG_CHG1
PE_CHG4
PE_CHG3
PE_CHG2
PE_CHG1
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
CoR
CoR
CoR
CoR
CoR
CoR
CoR
CoR
PGOOD change event for port 4
PGOOD change event for port 3
PGOOD change event for port 2
PGOOD change event for port 1
Power enable change event for port 4
Power enable change event for port 3
Power enable change event for port 2
Power enable change event for port 1
31
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